In storage devices (disk array systems and storage systems of this kind) of recent years, a cache memory is installed in a storage controller in order to increase the speed of reading and writing data. The cache memory holds a part of data to be written to a final storage medium such as a hard disk drive (hereinafter referred to as “HDD”) or a solid state disk (hereinafter referred to as “SSD”) or a part of data to be frequently read, thereby, hiding access latency of the medium and achieving a fast response to a host.
For example, when the host writes data to the storage device, a storage controller for processing the data provided in the storage device returns a write completion response to the host at the stage where the data is stored in the cache memory. Since the cache memory is much faster than a final storage medium, the host can issue the next I/O request immediately. Meanwhile, the storage controller operates so as to write the data in the cache memory to the final storage medium asynchronously with the operation of the host at a certain timing.
The storage controller is often configured of multiple controller units in order to improve fault tolerance. For this reason, cache memories (hereinafter, simply referred to as memories) are also arranged at multiple locations in a dispersed manner. For improvement in processing efficiency and redundancy by duplication, a data transfer is often executed between the memories. For such data transfer, a network path using an internal bus technology is formed between the controller units. For example, a standard such as PCI Express (registered trademark) is used for the bus. In addition, a data transfer controller called direct memory access (DMA) performs a data transfer between the cache memories according to a command by a processor executing storage control software.
In the case of PCI Express, so-called Posted Access is used in which the write request target does not issue a completion response (Completion) to the memory. In addition, buffers are provided on the path from the network path to the memory controller in the storage controller by reason of data processing by hardware. Accordingly, a source of write request cannot confirm whether or not data has passed through all the buffers on the path and has been written to the memory. For this reason, when data is written to a memory via a network path or the like, a dummy memory read request is issued via the same path in a storage device or the like to cause the buffers in the middle of the path to flush and then to ensure the writing of data to the memory. In PCI Express, a memory read request is called Non-Posted Access. The Non-Posted Access does not goes past Posted Access such as a memory write request and does not arrive at the memory before the Posted Access on the same path. Accordingly, if a response to the read request is returned, it is guaranteed that the write data according to the memory write request that has been issued in advance has passed through the buffers and has been written to the final memory.
Here, multiple network paths are set in some cases in order to secure a bandwidth because a transfer bandwidth achievable by a single path is limited. In order to efficiently perform a data transfer between multiple memories, it is necessary to evenly utilize the network paths. A technique to achieve load distribution through the network paths has been discussed heretofore as a method to eliminate unevenness and then to utilize the paths uniformly.
For example, Patent Literature (PTL) 1 discloses a method in which a hash value of a packet to be transferred is calculated, and a path is selected in accordance with the hash value. According to this method, the packet can be sent while the load is distributed to the multiple paths. Accordingly, the network transfer can be efficiently performed.